Gallium nitride material devices and methods of forming the same

ABSTRACT

The invention provides gallium nitride material devices, structures and methods of forming the same. The devices include a gallium nitride material formed over a substrate, such as silicon. Exemplary devices include light emitting devices (e.g., LED&#39;s, lasers), light detecting devices (such as detectors and sensors), power rectifier diodes and FETs (e.g., HFETs), amongst others.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.10/650,122, filed Aug. 25, 2003, and entitled “Gallium Nitride MaterialDevices and Methods of Forming the Same”, which is acontinuation-in-part of U.S. patent application Ser. No. 09/792,414 (nowU.S. Pat. No. 6,611,002), filed Feb. 23, 2001, and entitled “GalliumNitride Material Devices and Methods Including Backside Vias”. All ofthe above-mentioned disclosures are incorporated herein by reference.

FIELD OF INVENTION

The invention relates generally to semiconductor materials and, moreparticularly, to gallium nitride materials and methods of producinggallium nitride materials.

BACKGROUND OF INVENTION

Gallium nitride materials include gallium nitride (GaN) and its alloyssuch as aluminum gallium nitride (AlGaN), indium gallium nitride(InGaN), and aluminum indium gallium nitride (AlInGaN). These materialsare semiconductor compounds that have a relatively wide, direct bandgapwhich permits highly energetic electronic transitions to occur. Suchelectronic transitions can result in gallium nitride materials having anumber of attractive properties including the ability to efficientlyemit visible (e.g., blue, green) or UV light, the ability to transmitsignals at high frequency, and others. Accordingly, gallium nitridematerials are being widely investigated in many semiconductor deviceapplications such as transistors, field emitters, and optoelectronicdevices.

Gallium nitride materials have been formed on a number of differentsubstrates including silicon carbide (SiC), sapphire, and silicon.Silicon substrates are readily available and relatively inexpensive, andsilicon processing technology has been well developed. However, forminggallium nitride materials on silicon substrates to produce semiconductordevices presents challenges which arise from differences in the latticeconstant, thermal expansion, and band gap between silicon and galliumnitride.

SUMMARY OF INVENTION

The invention includes providing gallium nitride material structures,devices and methods of forming the structures and devices.

In one aspect, a semiconductor device is provided. The device comprisesa substrate, and a gallium nitride material region formed over thesubstrate. The semiconductor device has at least one via extending froma first side of the semiconductor device, wherein the via is free of anelectrical contact formed therein.

In another aspect, a method of forming a semiconductor device isprovided. The method comprises forming a gallium nitride material regionover a substrate, and forming a via extending from a first side of thesemiconductor device. The via is free of an electrical contact formedtherein.

In another aspect, a semiconductor device is provided. The semiconductordevice comprises a silicon substrate and a gallium nitride materialregion formed over the silicon substrate. The device further comprises afirst electrical contact formed over a portion of the gallium nitridematerial region, and a second electrical contact formed over a portionof the gallium nitride material region. The semiconductor device has atleast one via extending from a backside of the semiconductor device.

In another aspect, a method of forming a semiconductor device isprovided. The method comprises forming a gallium nitride material regionover a silicon substrate, forming a first electrical contact over thegallium nitride material region, and forming a second electrical contactover the gallium nitride material region. The method further comprisesforming a via extending from a backside of the semiconductor device.

In another aspect, an opto-electronic device is provided. Theopto-electronic device comprises a silicon substrate, acompositionally-graded transition layer formed over the siliconsubstrate, and a gallium nitride material region formed over thecompositionally-graded transition layer. The gallium nitride materialregion includes an active region.

In another aspect, a method of forming a opto-electronic device isprovided. The method comprises forming a compositionally-gradedtransition layer formed over a silicon substrate, and forming a galliumnitride material region over the compositionally-graded transitionlayer. The gallium nitride material region includes an active region.

In another aspect, a method of forming a semiconductor structure isprovided. The method comprises forming a first transition layer over asilicon substrate, forming a gallium nitride material region over thefirst transition layer, and removing the silicon substrate to expose abackside of the transition layer.

In another aspect, an opto-electronic device is provided. Theopto-electronic device comprises a transition layer comprising a galliumnitride alloy, aluminum nitride, or an aluminum nitride alloy. Thetransition layer has an exposed back surface. The device furthercomprises a gallium nitride material region formed over a front surfaceof the transition layer. The gallium nitride material region includes anactive region.

In another aspect, an opto-electronic device is provided. Theopto-electronic device comprises a transition layer comprising a galliumnitride alloy, aluminum nitride, or an aluminum nitride alloy. Thedevice further comprises an electrical contact formed directly on a backsurface of the transition layer, and a gallium nitride material regionformed over a front surface of the transition layer. The gallium nitridematerial region includes an active region.

In another aspect, an opto-electronic device is provided. Theopto-electronic device comprises a silicon substrate, a gallium nitridematerial region formed over the substrate. The gallium nitride materialregion includes an active region, wherein the active region has anon-rectangular plane-view cross-section.

In another aspect, an opto-electronic device is provided. Theopto-electronic device comprises a substrate, a gallium nitride materialregion formed over the substrate. The gallium nitride material regionincludes an active region, wherein the active region has anon-rectangular plane-view cross-section. A non-active region of theopto-electronic device has a non-rectangular plane-view cross-section.

In another aspect, a method is provided. The method comprises forming anactive region having a non-rectangular plane-view cross-section. Theactive region is a portion of a gallium nitride material region formedon a silicon substrate.

In another aspect, a method is provided. The method comprises forming anactive region having a non-rectangular plane-view cross-section. Theactive region is a portion of a gallium nitride material region formedon a substrate. The method further comprises forming a non-active regionhaving a non-rectangular plane-view cross-section.

Other aspects, embodiments and features of the invention will becomeapparent from the following detailed description of the invention whenconsidered in conjunction with the accompanying drawings. Theaccompanying figures are schematic and are not intended to be drawn toscale. In the figures, each identical, or substantially similarcomponent that is illustrated in various figures is represented by asingle numeral or notation. For purposes of clarity, not every componentis labeled in every figure. Nor is every component of each embodiment ofthe invention shown where illustration is not necessary to allow thoseof ordinary skill in the art to understand the invention. All patentapplications and patents incorporated herein by reference areincorporated by reference in their entirety. In case of conflict, thepresent specification, including definitions, will control.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a semiconductor device including a backside viaaccording to one embodiment of the present invention.

FIG. 2 illustrates a semiconductor device including multiple backsidevias according to another embodiment of the present invention.

FIG. 3 illustrates a semiconductor device including multiple backsidevias and no topside vias according to another embodiment of the presentinvention.

FIG. 4 illustrates an LED according to another embodiment of the presentinvention.

FIG. 5 illustrates a laser diode according to another embodiment of thepresent invention.

FIG. 6 illustrates a power rectifier diode according to anotherembodiment of the present invention.

FIG. 7 illustrates a double-gate HFET according to another embodiment ofthe present invention.

FIG. 8 illustrates an LED including multiple backside vias and notopside vias according to another embodiment of the present invention.

FIG. 9 illustrates a semiconductor device including a backside via freeof an electrical contact according to another embodiment of the presentinvention.

FIG. 10 illustrates a semiconductor device including a backside viahaving a backside via that is shaped to enhance internal reflection oflight according to another embodiment of the present invention.

FIG. 11 illustrates a semiconductor device including a positive andnegative contact formed on a backside of the device according to anotherembodiment of the present invention.

FIG. 12 illustrates a semiconductor device after the substrate has beenremoved during processing according to another embodiment of the presentinvention.

FIG. 13 illustrates a light emitting device that includes two topsidecontacts according to another embodiment of the present invention.

FIG. 14 illustrates a light emitting device including two topsidecontacts according to another embodiment of the present invention.

FIG. 15 illustrates a light emitting device after the substrate has beenremoved during processing according to another embodiment of the presentinvention.

FIG. 16 illustrates a light emitting device including a reflector regionaccording to another embodiment of the present invention.

FIG. 17 illustrates a light emitting device including a reflector regionaccording to another embodiment of the present invention.

FIG. 18 illustrates a light emitting device including a mediumcontaining phosphor according to another embodiment of the presentinvention.

FIG. 19 illustrates a light emitting device including a reflector regionformed within a via according to another embodiment of the presentinvention.

FIG. 20 illustrates a light emitting device that has been flipped duringuse according to another embodiment of the present invention.

FIG. 21 illustrates an LED designed to emit UV light according toanother embodiment of the present invention.

FIG. 22 illustrates a view of a backside the device of FIG. 1.

FIGS. 23A-23K illustrate a series of plane-view cross-sections ofrespective active regions of opto-electronic devices according toadditional embodiments of the invention.

FIG. 24 illustrates an opto-electronic device including an active regionaccording to another embodiment of the invention.

FIG. 25 illustrates a light emitting device that is mounted to a carrieraccording to another embodiment of the present invention.

FIG. 26 illustrates a semiconductor device according to an embodiment ofthe invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention provides gallium nitride material structures, devices andmethods of forming the structures and devices.

Referring to FIG. 1, a semiconductor device 10 according to oneembodiment of the invention is shown. Semiconductor device 10 includes asubstrate 12 and a gallium nitride material device region 14 formed overthe substrate. As described further below, device structures aretypically formed, at least in part, within gallium nitride materialregion 14. Device 10 further includes a transition layer 15 formed onsubstrate 12, for example, to facilitate the subsequent deposition ofgallium nitride material device region 14. In some cases, the transitionlayer (or, at least a portion of the transition layer) may benon-conducting. A topside electrical contact 16 (on a topside 18 of thedevice) and a backside electrical contact 20 (on a backside 22 of thedevice) are provided for connection to an external power supply thatpowers the device. Backside contact 20 is deposited within a via 24 thatextends from backside 22 of the device. Via 24 extends throughtransition layer 15 and into a conducting region (e.g., device region14) within device 10. As a result of the deposition of backside contact20 within via 24, current can flow between the backside contact andtopside contact 16 through device region 14 without being blocked bytransition layer 15, when the transition layer is non-conducting. Thus,vertical conduction through device 10 between backside contact 20 andtopside contact 16 may be achieved despite the presence of anon-conducting transition layer 15.

FIG. 22 illustrates a view of backside 22 of device 10.

As used herein, “non-conducting” refers to a layer that prevents currentflow or limits current flow to negligible amounts in one or moredirections. “Non-conducting” layers, for example, may be formed ofnon-conductor materials, or may be formed of semiconductor materialswhich have a band sufficiently offset from the layer adjacent the“non-conducting” layer. A “non-conducting” layer may be conductive inand of itself, but may still be non-conducting (e.g., in a verticaldirection) as a result of a band offset or discontinuity with anadjacent layer. As used herein, “vertical conduction” refers toelectrical current flow in a vertical direction within a device.“Vertical conduction” may be between backside contact and topsidecontact or may be between different layers within the device that areseparated vertically.

It should be understood that when a layer is referred to as being “on”or “over” another layer or substrate, it can be directly on the layer orsubstrate, or an intervening layer also may be present. A layer that is“directly on” another layer or substrate means that no intervening layeris present. It should also be understood that when a layer is referredto as being “on” or “over” another layer or substrate, it may cover theentire layer or substrate, or a portion of the layer or substrate.

As shown in the figures, the term “topside” refers to the upper surfaceof a structure or device and the term “backside” refers to the bottomsurface of a structure or device. It should be understood that thesubstrate also has a “topside” and a “backside.” When processing atypical structure, layer(s) are grown from the topside of the substrateand the resulting upper growth surface defines the topside of thestructure or device. In some cases, during use, a device may be flippedso that its backside faces upward and its topside faces downward (e.g.,See FIG. 20). In these “flip chip” embodiments, the topside of thedevice may be mounted to another surface (e.g., to provide a source ofpower to electrodes on the topside).

In certain preferred embodiments, substrate 12 is a silicon substrate.As used herein, silicon substrate 14 refers to any substrate thatincludes a silicon layer. Examples of suitable silicon substratesinclude substrates that are composed entirely of silicon (e.g., bulksilicon wafers), silicon-on-insulator (SOI) substrates,silicon-on-sapphire substrate (SOS), and SIMOX substrates, amongstothers. Suitable silicon substrates also include substrates that have asilicon wafer bonded to another material such as diamond, AlN, or otherpolycrystalline materials. Silicon substrates having differentcrystallographic orientations may be used. In some cases, silicon (111)substrates are preferred. In other cases, silicon (100) substrates arepreferred.

It should be understood that in other embodiments, substrates other thansilicon substrates may be used such as sapphire and silicon carbidesubstrates.

Substrate 12 may have any suitable dimensions and its particulardimensions are dictated by the application. Suitable diameters include,but are not limited to, 2 inches (50 mm), 4 inches (100 mm), 6 inches(150 mm), and 8 inches (200 mm). In some embodiments, silicon substrate12 is relatively thick, for example, greater than 250 microns. Thickersubstrates are generally able to resist bending which can occur, in somecases, in thinner substrates. In some embodiments, silicon substrate 12is preferably thin, for example less than 250 microns, or less than 100microns, to facilitate the formation of via 24 therethrough.

Transition layer 15 may be formed on substrate 12 prior to thedeposition of gallium nitride material device region 14, for example, toaccomplish one or more of the following: reducing crack formation ingallium nitride material device region 14 by lowering thermal stressesarising from differences between the thermal expansion rates of galliumnitride materials and the substrate; reducing defect formation ingallium nitride material device region 14 by lowering lattice stressesarising from differences between the lattice constants of galliumnitride materials and the substrate; and, increasing conduction betweensubstrate 12 and gallium nitride material device region 14 by reducingdifferences between the band gaps of substrate 12 and gallium nitridematerials. The presence of transition layer 15 may be particularlypreferred when utilizing silicon substrates because of the largedifferences in thermal expansion rates and lattice constant betweengallium nitride materials and silicon. It should be understood thattransition layer 15 also may be formed between substrate 12 and galliumnitride material device region for a variety of other reasons. As notedabove, transition layer 15 may be non-conducting, although, in somecases, transition layer 15 may be conducting.

The composition of transition layer 15 depends, at least in part, uponthe type of substrate and the composition of gallium nitride materialdevice region 14. In some embodiments which utilize a silicon substrate,transition layer 15 may preferably comprise a compositionally-gradedtransition layer having a composition that is varied across at least aportion of the layer. Suitable compositionally-graded transition layers,for example, have been described in co-pending, commonly-owned, U.S.patent application Ser. No. 09/736,972, entitled “Gallium NitrideMaterials and Methods,” filed on Dec. 14, 2000, which is incorporatedherein by reference. Compositionally-graded transition layers areparticularly effective in reducing crack formation in gallium nitridematerial device region 14 by lowering thermal stresses that result fromdifferences in thermal expansion rates between the gallium nitridematerial and substrate 12 (e.g., silicon). In some embodiments, whencompositionally-graded, transition layer 15 is formed of an alloy ofgallium nitride such as Al_(x)In_(y)Ga_((1-x-y))N, Al_(x)Ga_((1-x))N, orIn_(y)Ga_((1-y))N. In these embodiments, the concentration of at leastone of the elements (e.g., Ga, Al, In) of the alloy is typically variedacross at least a portion of the cross-sectional thickness of the layer.

In other embodiments, transition layer 15 has a constant (i.e.,non-varying) composition across its thickness. Such layers may bereferred to as buffer layers and/or intermediate layers. Suitableintermediate layers, for example, have been described in U.S. patentapplication Ser. No. 09/736,972, referenced above. In some embodiments,transition layer 15 has a constant composition of a gallium nitridealloy (such as Al_(x)In_(y)Ga_((1-x-y))N, Al_(x)Ga_((1-x))N, orIn_(y)Ga_((1-y))N), aluminum nitride, or an aluminum nitride alloy.

In the illustrative embodiment of FIG. 1, a single transition layer 15is shown between substrate 12 and gallium nitride material device region14. Other embodiments may include more than one transition layer. Forexample, as shown in FIG. 2, device 10 a may include acompositionally-graded transition layer 15 a formed on (in some cases,directly on) a transition layer 15 b having a constant composition(e.g., an intermediate layer of a gallium nitride alloy, aluminumnitride, or an aluminum nitride alloy). It should also be understoodthat constant composition transition layer 15 b may be formed on (insome cases, directly on) compositionally-graded transition layer 15 a.In some cases, the device may include two constant compositiontransition layers—for example, a first formed on thecompositionally-graded transition layer and a second formed on thesubstrate under the compositionally-graded transition layer.

It also should be understood that in some embodiments, one or more othertypes of layers (including conducting layers) may be present betweensubstrate 12 and gallium nitride material device region 14 which mayaccomplish one or more of the above-described features of the transitionlayer. In some cases, the transition layer is the sole layer between thesubstrate and the gallium nitride material device region. Inembodiments, that include one or more conducting layer, the structuremay not include any non-conducting layers.

In the embodiment of FIG. 1, via 24 extends through transition layer 15of substrate 12 so that vertical conduction can occur in device 10 evenwhen the transition layer is non-conducting. Thus, in these embodiments,at a minimum, via 24 has a length (L) sufficient to create a conductingvertical path between topside contact 16 and backside contact 20. Via24, for example, may extend to a position within gallium nitridematerial device region 14 to form such a conducting path. In some cases,it may be preferable to have via 24 extend to an etch-stop layer (e.g.,See 46, FIG. 5) within gallium nitride material device region 14, tofacilitate processing as described further below. In certainembodiments, via 24 may extend to a position below gallium nitridematerial device layer—for example, within an upper portion of a doped,conductive transition layer and, thus, a vertical conducting path isformed. In some cases, via 24 may extend to a source region or a drainregion formed within device 10.

The exact dimensions and shape of via 24 depend upon the application. Atypical cross-sectional area of via is about 100 microns by about 100microns at backside 22. The cross-sectional area of the via may besquare (as shown in FIG. 22), circular or another shape. It may bepreferable for via 24 to be tapered inward, as shown, thus giving thevia a cone shape (i.e., a truncated pyramid shape). The inward taper(i.e., a cross-sectional area that decreases in a direction away fromthe backside) can facilitate deposition of backside contact 20 on sidewalls 28 of via 24 and may also, in some cases, be beneficial forenhancing light extraction. In other cases, as described further belowand shown in FIG. 10, it may be preferable for the via to be taperedoutward (i.e., a cross-sectional area that increases in a direction awayfrom the backside). An outwardly tapered via may enhance internal lightreflection which can improve light extraction in certain embodiments. Insome cases, it may be preferable to have via 24 positioned away fromsides 29 of the device. That is, the via does not intersect with a sideof the device.

In FIG. 1, device 10 includes a single via 24. Other embodiments,however, as described further below and shown in FIGS. 2-3, may includemore than one via.

As used herein, the phrase “electrical contact” or “contact” refers toany conducting structure on a semiconductor device that is designed tobe contacted by a power source. “Contacts” may also be referred to aselectrodes, terminals, contact pads, contact areas, contact regions andthe like. It should be understood that certain types of conductingstructures that are on, or part of, a semiconductor device are notelectrical contacts, as used herein. For example, conducting regions orlayers (e.g., reflector layer 120 in some cases) that are not contactedby a power source during use are not electrical contacts as definedherein.

Backside contact 20 and topside contact 16 are formed of conductingmaterials including certain metals. Any suitable conducting materialknown in the art may be used. The composition of contacts 16, 20 maydepend upon the type of contact. For example, contacts 16, 20 maycontact n-type material or p-type material. Suitable metals for n-typecontacts include titanium, nickel, aluminum, gold, copper, and alloysthereof. Suitable metals for p-type contacts include nickel, gold, andtitanium, and alloys thereof.

Contacts 16, 20 have a thickness sufficient to ensure that the contactis electrically conductive across its entire physical area. Suitablethicknesses for contacts 16, 20, for example, are between about 0.05microns and about 10 microns. In some cases, the thickness of backsidecontact 20 may vary over its area because of uneven deposition on sidewalls 28 of via 24. The surface areas of backside contact 20 and topsidecontact 16 are generally sufficient so that the contacts can becontacted by terminals of an appropriate power source through wirebonding, air bridging and the like. In certain preferred embodiments,backside contact 20 substantially extends only over backside and doesnot, for example, extend over sides 30 of device 10. Thus, in thesepreferred embodiments, sides 30 are substantially free of backsidecontact 20.

In some embodiments, as described further below, semiconductor structuremay include one or more backside contact and no topside contact (e.g.,FIG. 3), or one or more topside contact (e.g., two for light emittingdevices or three for FETs) and no backside contact (e.g., FIGS. 13-16).

In some embodiments, contacts 16, 20 also may function as an effectiveheat sink. In these embodiments, contacts 16, 20 remove thermal energygenerated during the operation of the device. This may enable device 10to operate under conditions which generate amounts of heat that wouldotherwise damage the device. In particular, laser diodes that operate athigh current densities may utilize contacts 16, 20 as a heat sink.Contacts 16, 20 may be specifically designed to enhance thermal energyremoval. For example, contacts 16, 20 may be composed of materials suchas copper and gold, which are particularly effective at removing heat.Also, contacts 16, 20 may be designed so that a large surface area is incontact with device region 14 for example, by including multiple viasand/or vias that extend significantly into device region 14.

In some embodiments, such as when device 10 is an opto-electronicdevice, contacts 16, 20 can function as a reflector region (e.g., 120 a,FIG. 19), as described further below. By reflecting light generated bythe device, contacts 16, 20 can direct the light in a desired direction,for example, out of topside 18, backside 22, and/or sides 30 of device10 depending on the design of the device. Thus, the output efficiency ofthe device may be enhanced. In particular, laser diodes and lightemitting diodes can benefit from utilizing the reflective properties ofcontacts 16, 20. To enhance the ability of backside contact 20 toreflect light, for example, via 24 is formed such that the backsidecontact extends proximate an active region (e.g., 38, FIG. 4; 50, FIG.5).

As used herein, the term “active region,” when used in connection with alight emitting device, refers to a light generating region, and whenused in connection with a light detecting device refers to a lightcollecting region.

In certain embodiments, and as described further below in connectionwith FIGS. 9-11, 13-14, and 16-18, it may be preferable for via 24 to befree of a contact. That is, a contact is not formed within the via. Insome cases, the via may be free of a contact but may have one or moreother region(s) or layer(s) formed therein (e.g., a reflective layer),as described further below. In some cases, the via may be free of anymaterial formed therein. When free of material, the via may function asa window that exposes internal layers of the device (e.g., transitionlayer 15 or gallium nitride material device region 14) to the outside.This exposure may enhance the extraction of light from the device whichcan be particularly useful in light-emitting devices such as LEDs orlasers. In embodiments in which via 24 is free of an electrical contact,it should be understood that contacts are formed on other parts of thedevice including other (non-via) areas of backside 22 or areas oftopside 18.

In some cases, to maximize exposure of the internal device layers,substrate 12 may be entirely removed, for example, by etching (wet ordry) or grinding. Such a device is shown in FIGS. 12, 15 and 25, anddescribed further below. When the substrate is entirely removed, it maybe desirable to mount, or bond, the structure to a carrier which may bea wafer (e.g., silicon or GaAs) that provides rigidity and/or supportduring further processing, handling, or use. The rigidity and/or supportprovided by the carrier result from its relatively large thicknesscompared to the thickness of the remaining structure. In some cases,carriers may also function as a reflector region.

Gallium nitride material device region 14 comprises at least one galliumnitride material layer. In some cases, gallium nitride material deviceregion 14 includes only one gallium nitride material layer. In othercases, as described further below and shown in FIGS. 4-8, galliumnitride material device region 14 includes more than one gallium nitridematerial layer. The different layers can form different regions of thesemiconductor structure. Gallium nitride material region 14 also mayinclude one or more layers that do not have a gallium nitride materialcomposition such as other III-V compounds or alloys, oxide layers, andmetallic layers.

As used herein, the phrase “gallium nitride material” refers to galliumnitride (GaN) and any of its alloys, such as aluminum gallium nitride(Al_(x)Ga_((1-x))N), indium gallium nitride (In_(y)Ga_((1-y))N),aluminum indium gallium nitride (Al_(x)In_(y)Ga_((1-x-y))N), galliumarsenide phosphoride nitride (GaAs_(a)P_(b) N_((1-a-b))), aluminumindium gallium arsenide phosphoride nitride(Al_(x)In_(y)Ga_((1-x-y))As_(a)P_(b)N_((1-a-b))), amongst others.Typically, when present, arsenic and/or phosphorous are at lowconcentrations (i.e., less than 5 weight percent). In certain preferredembodiments, the gallium nitride material has a high concentration ofgallium and includes little or no amounts of aluminum and/or indium. Inhigh gallium concentration embodiments, the sum of (x+y) may be lessthan 0.4, less than 0.2, less than 0.1, or even less. In some cases, itis preferable for the gallium nitride material layer to have acomposition of GaN (i.e., x+y=0). Gallium nitride materials may be dopedn-type or p-type, or may be intrinsic. Suitable gallium nitridematerials have been described in U.S. patent application Ser. No.09/736,972, incorporated herein.

Gallium nitride material region 14 is of high enough quality so as topermit the formation of devices therein. Preferably, gallium nitridematerial region 14 has a low crack level and a low defect level. Asdescribed above, transition layer 15 may reduce crack and/or defectformation. In some embodiments, gallium nitride material region 14 hasabout 10⁹ defects/cm². Gallium nitride materials having low crack levelshave been described in U.S. patent application Ser. No. 09/736,972,referenced above. In some cases, gallium nitride material region 14 hasa crack level of less than 0.005 μm/μm². In some cases, gallium nitridematerial has a very low crack level of less than 0.001 μm/μm². Incertain cases, it may be preferable for gallium nitride material region14 to be substantially crack-free as defined by a crack level of lessthan 0.0001 μm/μm².

In certain cases, gallium nitride material region 14 includes a layer orlayers which have a monocrystalline structure. In some preferred cases,gallium nitride material region 14 includes one or more layers having aWurtzite (hexagonal) structure.

The thickness of gallium nitride material device region 14 and thenumber of different layers are dictated, at least in part, by therequirements of the specific application. At a minimum, the thickness ofgallium nitride material device region 14 is sufficient to permitformation of the desired device. Gallium nitride material device region14 generally has a thickness of greater than 0.1 micron, though notalways. In other cases, gallium nitride material region 14 has athickness of greater than 0.5 micron, greater than 0.75 micron, greaterthan 1.0 microns, greater than 2.0 microns, or even greater than 5.0microns.

When device 10 is a light-emitting device, it may also include areflector region 120 (See FIG. 16). Reflector region 120 increases thereflectivity of an interface and typically directs or steers the lightin a desired location or direction within a light-emitting device. Thecomposition and structural characteristics (e.g., thickness) of thereflector region may be selected to reflect the desired wavelength (orrange or wavelengths) of light.

Reflector region 120 may be a single layer or a series of layers. Insome cases, reflector region 120 comprises a metal. In other cases,reflector region 120 may comprise a dielectric or semiconductormaterial. In these cases, typically, multiple dielectric orsemiconductor material layers are stacked to form the reflector region.One example of a multi-layer reflector region is a Distributed BraggReflector (DBR). A DBR has at least two layers of different compositions(e.g., gallium nitride alloys or oxide-based compounds).

The location of the reflector region in the device is selected so as toreflect light in the desired direction. Typically, the position of thereflector region is selected relative to the light emitting region(s) ofthe device. For example, if it is desired to reflect light in thedirection of the backside of the device, reflector region 120 ispreferably located above an active region (e.g., 97, FIG. 17) in whichlight is generated. If it is desired to reflect light in the directionof the topside of the device, reflector region 120 is preferably locatedbelow the active region (e.g., 97, FIG. 16). In some cases, such as whenthe device is a laser, reflector region 120 may located both above andbelow an active region. Depending on the device design, reflector region120 may be a portion of the gallium nitride material region 14, or maybe located above or below the gallium nitride material region. As notedabove, in some cases, reflector region 120 may be an electrical contact,though other types of electrical contacts are not reflector regions. Inembodiments in which the reflector region also functions as anelectrical contact, the reflector region, for example, may be formed ofaluminum, silver or rhodium.

Device 10 may be formed using known processing techniques. Transitionlayer 15 and gallium nitride material device region 14 may be depositedon substrate 12, for example, using metalorganic chemical vapordeposition (MOCVD), molecular beam epitaxy (MBE), and hydride vaporphase epitaxy (HVPE), amongst other techniques. In some cases, an MOCVDprocess may be preferred. A suitable MOCVD process to form acompositionally-graded transition layer 15 and gallium nitride materialdevice region 14 over a silicon substrate 12 has been described in U.S.patent application Ser. No. 09/736,972, referenced above. When galliumnitride material device region 14 has different layers, in some cases itis preferable to use a single deposition step (e.g., an MOCVD step) toform the entire device region 14. When using the single deposition step,the processing parameters are suitably changed at the appropriate timeto form the different layers. In certain preferred cases, a singlegrowth step may be used to form transition layer 15 and gallium nitridematerial device region 14.

When present, reflector region 120 may also be formed using knownprocessing techniques. For example, when the reflector region comprisesa metal, the metal may be sputtered or evaporated. When the reflectorregion comprises a series of semiconductor material layers, the layersmay be deposited using metalorganic chemical vapor deposition (MOCVD),molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE),amongst other techniques. When the reflector region comprises a seriesof dielectric material layers, the layers may be deposited by chemicalvapor deposition (CVD) or sputtering.

In some cases, it may be preferable to grow device region 14 using alateral epitaxial overgrowth (LEO) technique that involves growing anunderlying gallium nitride layer through mask openings and thenlaterally over the mask to form the gallium nitride material deviceregion, for example, as described in U.S. Pat. No. 6,051,849, which isincorporated herein by reference. In some cases, it may be preferable togrow device region 14 using a pendeoepitaxial technique that involvesgrowing sidewalls of gallium nitride material posts into trenches untilgrowth from adjacent sidewalls coalesces to form a gallium nitridematerial region, for example, as described in U.S. Pat. No. 6,177,688,which is incorporated herein by reference. In these lateral growthtechniques, gallium nitride material regions with very low defectdensities are achievable. For example, at least a portion of galliumnitride material region 14 may have a defect density of less than about10⁵ defects/cm².

Conventional etching techniques may be used to form via 24. Suitabletechniques include wet chemical etching and plasma etching (i.e., RIE,ICP etching, amongst others). Different etching techniques may beutilized when etching through different layers of device 10. Forexample, a fluorine-based RIE process may be used to etch throughsubstrate 12 and a chlorine-based RIE process may be used to etchthrough gallium nitride device region 14 and/or transition layer 15. Apre-determined etching time may be used to form via 24 with the desireddimensions. In other cases, an etch stop layer (e.g., See 46, FIG. 5),which has a composition that is not readily etched by the techniquebeing used, may be provided within device 10 to stop etching so thatprecise control over the etching time is not required to form via 24with desired dimensions.

Backside contact 20 and topside contact 16 may be deposited using knowntechniques suitable for depositing conducting materials such as metals.Such techniques include sputtering, electron beam deposition, andevaporation, amongst others. In some cases, a series of layers havingdifferent metallic compositions are deposited successively to formcontacts 16, 20. In some of these cases, an annealing technique is usedto yield equilibration of the contact composition. Because backsidecontact 20 is deposited within via 24, the deposition technique shouldbe performed in a manner that provides sufficient coverage within via24.

As known in the semiconductor art, multiple device structures may beformed on the same wafer of substrate material. A dicing operation,which utilizes a saw, may be used to separate individual devices fromone another. In embodiments using silicon substrates, devices may beseparated in an etching process (e.g., wet or dry) which etches throughthe substrate and layers. This etching process may use different etchchemistries when etching through different layers of the structure andsubstrate. For example, a fluorine-based gas may be used to etch throughthe silicon substrate and a chlorine-based gas may be used to etchthrough gallium nitride device region 14 and/or transition layer 15.Separation using an etching process can enable formation of deviceshaving non-rectangular die shapes (See FIGS. 23C-23K) which may beadvantageous in certain light emitting applications, as describedfurther below.

FIG. 2 illustrates device 10 a which includes multiple vias 24 a, 24 baccording to another embodiment of the present invention. A singlebackside contact 20 is formed in and across both vias 24 a, 24 b. Usingmultiple vias 24 a, 24 b as shown in FIG. 2 may enhance heat removal,improve light reflection, and increase vertical conduction. As notedabove, device 10 a also includes a compositionally-graded transitionlayer 15 a formed on a constant composition transition layer 15 b. Itshould be understood that device 10 a is not limited to this transitionlayer arrangement and that other transition layer(s) described hereinare possible including a single transition layer.

FIG. 3 illustrates device 10 b including multiple vias 24 a, 24 baccording to another embodiment of the present invention. A firstbackside contact 20 a is formed in via 24 a and a second backsidecontact 20 b is formed in via 24 b. A dielectric layer 31 may be used,for example, to electrically isolate portions of backside contact 20 bto prevent shorting of device 10. Suitable compositions for dielectriclayer 31 include silicon oxide and silicon nitride. The embodiment ofFIG. 3 does not have a topside contact (16 in FIG. 1). The embodiment ofFIG. 3 may be utilized in cases when it is not desirable to have atopside contact such as for surface mounted devices.

It should be understood that the invention also includes devices havingbackside vias and backside contacts with other configurations than thoseillustrated herein. For example, backside contact 20 may extend to anactive region within gallium nitride material device region 14, such asa source region or a drain region. Also, backside contact 20 may extendsubstantially through the thickness of the device so that the backsidecontact also forms a contact on topside 18 of the device.

It should also be understood that certain embodiments of the inventiondo not include a backside contact 20 as shown in FIG. 13. Device 110includes a first topside contact 16 d and a second topside contact 16 e.As shown, first topside contact 16 d is formed on a first topsideportion 18 a of gallium nitride material region 14 and second topsidecontact 16 e is formed on a second topside portion 18 b of the galliumnitride material region, wherein the first topside portion and thesecond topside portion are on different planes. In other cases, firstand second topside contacts are formed on the same plane. It may beadvantageous to include multiple topside contacts and no backsidecontacts, for example, when the topside of the device is mounted to asurface (e.g., in flip-chip embodiments). Also, it may be advantageousto include multiple topside contacts and no backside contacts in certainlight emitting devices (e.g., LEDs, lasers) when it is desired to emitlight out of the backside of the device. The absence of a backsidecontact, and/or any other material, in backside via 24 of device 110 canenhance light emission, amongst other advantages.

It should be understood that devices of the invention may include morethan two (e.g., three contacts) topside contacts in certain deviceconfigurations (e.g., FETs)

FIG. 18 illustrates a light-emitting device 124 that includes a medium126 comprising phosphor. The medium, for example, may include phosphordispersed in epoxy. The phosphor may convert light generated within thedevice to light of a different wavelength. For example, phosphor may beused to convert blue or UV-light generated within the device to whitelight. It should be understood that light emitting device 124 may haveany suitable layer arrangement including layer arrangements of the LEDembodiments described herein

Any suitable semiconductor device known in the art including electronicand opto-electronic devices may utilize features of the invention. Inmany cases, the device may be formed entirely within gallium nitridematerial region 14 (i.e., the only active device regions are withingallium nitride material region 14). In other cases, the device isformed only in part within gallium nitride material region 14 and isalso formed in other regions such as substrate 12.

Exemplary devices include light emitting devices (such as laser diodes(LDs) and light emitting diodes (LEDs)), light detecting devices (suchas detectors and sensors), power rectifier diodes, FETs (e.g., HFETs),Gunn-effect diodes, varactor diodes, amongst others. Light-emittingdevices of the invention may be designed to emit the desired wavelengthof light including visible light (e.g., blue) and UV-light. As describedabove, the device may also include one or more types of phosphor thatconverts the light generated within the device to white light. Althoughcertain figures may illustrate certain types of devices, it should beunderstood that the features of these figures may also be used in othertypes of devices of the present invention. For example, though FIGS.13-20 illustrate light emitting devices, it should be understood thatfeatures of these figures may also be used in light detecting devices.In such light detecting devices, active region 97 is a light collectorregion, in contrast to the light generating region shown in some ofthese figures.

FIGS. 4-8 illustrate examples of gallium nitride material devicesaccording to the invention. It should be understood, however, thatdevices having other structures are also within the scope of theinvention.

FIG. 4 illustrates an exemplary LED 32 according to one embodiment ofthe present invention. LED 32 includes gallium nitride material deviceregion 14 formed on transition layer 15. Transition layer 15 may becompositionally-graded and is formed on silicon substrate 12. In theillustrative embodiment, the following layers comprise gallium nitridematerial device region 14 in succession: a silicon-doped GaN layer 34, asilicon-doped Al_(x)Ga_((1-x))N layer 36 (e.g., containing 0-20% byweight Al), a GaN/InGaN single or multiple quantum well 38, amagnesium-doped Al_(x)Ga_((1-x))N layer 40 (e.g., containing 10-20% byweight Al), and a magnesium-doped GaN layer 41. Via 24 extends frombackside 22 to a position within GaN layer 34. Topside contact 16 isformed of a metal on a p-type region and backside contact 20 is formedof a metal on an n-type region. LED 32 may be provided as a variety ofdifferent structures including: a double heterostructure (e.g., Al>0% inlayer 36), a single heterostructure (e.g., Al=0% in layer 36), asymmetric structure, or an asymmetric structure. The LED illustrated inthis embodiment is designed to emit visible light (e.g., blue light). Itshould be understood that LEDs having a variety of different structuresmay also be provided according to the invention including LEDs that emitUV light (See FIG. 21).

FIG. 5 illustrates an exemplary laser diode 42 according to oneembodiment of the present invention. Laser diode 42 includes galliumnitride material device region 14 formed on transition layer 15.Transition layer 15 may be compositionally-graded and is formed onsilicon substrate 12. In the illustrative embodiment, the followinglayers comprise gallium nitride material device region 14 in succession:a silicon-doped GaN layer 44, a silicon-doped Al_(x)Ga_((1-x))N layer 46(e.g., containing 5-30% by weight Al), a silicon-doped Al_(x)Ga_((1-x))Nlayer 48 (e.g., containing 0-20% by weight Al), a GaN/InGaN single ormultiple quantum well 50, a magnesium-doped Al_(x)Ga_((1-x))N layer 52(e.g., containing 5-20% by weight Al), a magnesium-dopedAl_(x)Ga_((1-x))N layer 54 (e.g., containing 5-30% by weight Al), and amagnesium-doped GaN layer 55. Via 24 extends from backside 22 toAl_(x)Ga_((1-x))N layer 46 which functions as an etch-stop layer.Topside contact 16 is formed of a p-type metal and backside contact 20is formed of an n-type metal. It should be understood that laser diodeshaving a variety of different structures may also be provided.

FIG. 6 illustrates a power rectifier diode 56 according to oneembodiment of the present invention. Diode 56 includes gallium nitridematerial device region 14 formed on transition layer 15. Transitionlayer 15 may be compositionally-graded and is formed on siliconsubstrate 12. In the illustrative embodiment, the following layerscomprise gallium nitride material device region 14 in succession: asilicon-doped GaN layer 58 and an intrinsic GaN layer 60. Via 24 extendsfrom backside 22 to a position within GaN layer 58. Topside contact 16is formed of a rectifying metal and backside contact 20 is formed of ann-type metal. It should be understood that diodes having a variety ofdifferent structures may also be provided.

FIG. 7 illustrates a double-gated HFET 64 according to one embodiment ofthe present invention. HFET 64 includes gallium nitride material deviceregion 14 formed on transition layer 15. Transition layer 15 may becompositionally-graded and is formed on silicon substrate 12. In theillustrative embodiment, the following layers comprise gallium nitridematerial device region 14 in succession: an intrinsic GaN layer 66 andan intrinsic AlGaN region 68. Via 24 extends from backside 22 to aposition within GaN layer 66. HFET 64 includes a source topside contact16 a, a gate topside contact 16 b, and a drain topside contact 16 c. Abackside gate contact 20 is formed within via 24. It should beunderstood that HFETs having a variety of different structures may alsobe provided including HFETs having a plurality of gates.

FIG. 8 illustrates an LED 70 including multiple backside vias 24 a, 24 baccording to another embodiment of the present invention. LED 70includes gallium nitride material device region 14 formed on transitionlayer 15. Transition layer 15 may be compositionally-graded and isformed on silicon substrate 12. In the illustrative embodiment, thefollowing layers comprise gallium nitride material device region 14 insuccession: a silicon-doped GaN layer 72, a silicon-dopedAl_(x)Ga_((1-x))N layer 74 (e.g., containing 0-20% by weight Al), aGaN/InGaN single or multiple quantum well 76, a magnesium-dopedAl_(x)Ga_((1-x))N layer 78 (e.g., containing 10-20% by weight Al), and amagnesium-doped GaN layer 80. Via 24 a extends from backside 22 to aposition within GaN layer 72 and via 24 b extends from backside 22 to aposition within GaN layer 80. An n-type backside contact 20 a is formedwithin via 24 a and a p-type backside contact 20 b is formed within via24 b. A dielectric layer 31 isolates portions of p-type backside contact20 b to prevent shorting. It should be understood that LEDs having avariety of different structures may also be provided.

FIG. 9 illustrates a device 82 including backside via 24 that is free ofan electrical contact according to another embodiment of the presentinvention. Device 82 includes gallium nitride material device region 14formed on a transition layer 15. Device may have any suitable layerarrangement including the layer arrangements (or a portion thereof) ofthe LED embodiments described herein. Transition layer 15 can becompositionally-graded, as described above. Via 24 extends from backside22 to transition layer 15, thus, exposing the transition layer to theenvironment. An n-type contact 20 is formed on backside 22.

FIG. 10 illustrates a device 96 including a backside via 24 having across-sectional area that increases in a direction away from backside22. Device 96 may have any suitable layer arrangement including thelayer arrangements (or a portion thereof) of the LED embodimentsdescribed herein. In the illustrative embodiment, device 96 is a lightemitting device that includes an active region 97 in which light isgenerated, though other devices of the invention may also include abackside via having this shape. This via shape may enhance internallight reflections (as indicated by the arrows) and external lightextraction from the topside of the device. In some cases, and as shown,device 96 may be mounted on a reflective surface 98 to further enhancelight reflection and/or a reflector region 120 may be formed on walls ofthe via. Reflective surface 98, for example, may be the surface of apackaging material or a carrier.

FIG. 11 illustrates a device 100 according to another embodiment of theinvention. Device 100 includes a number of contacts 102 formed on thefront and back of substrate 12. As shown, device 100 includes the samelayer arrangement as the LED of FIG. 8, though other suitable layerarrangements are also possible. LED 100 also includes an n-type contact104 and a p-type contact 106. A dielectric layer 31 isolates portions ofthe n-type and p-type contacts to prevent shorting.

FIG. 12 illustrates a device 108 according to another embodiment of thepresent invention. Device 108 has the same layer arrangement as thedevice of FIG. 11 except that, during processing, the entire substratehas been removed using an etching step. Other layer arrangements may beused. The entire backside of transition layer 15, which may becompositionally-graded or have a constant composition, is exposed to theenvironment. This embodiment may be particular useful in order tomaximize light extraction from the device. It should be understood thatother devices of the present invention, including non-light emittingdevices, may also be processed by removing the entire substrate. Itshould also be understood that devices which include an exposedtransition layer (e.g., a compositionally-graded transition layer) mayalso be used in devices that include two topside contacts, for example,as shown in FIG. 13. A topside or a backside of device 108 may bemounted on, or bonded to, a carrier (not shown). The carrier, which maybe a wafer (e.g., silicon or GaAs), can provide support and rigidity forthe device that may be desirable in the absence of the originalsubstrate.

FIG. 14 illustrates a light emitting device 112 according to anotherembodiment of the invention. Device 112 includes an active region 97 andmay have any suitable layer arrangement including the layer arrangements(or a portion thereof) of the LED embodiments described herein. Device112 has two topside contacts 114 a, 114 b and no backside contacts.Arrows indicate the direction of light. The topside contacts alsofunction as reflector regions which reflect, at least a portion of thelight generated in layer 97. In this embodiment, light is emitted out ofthe backside of the device.

FIG. 15 illustrates a light emitting device 116 according to anotherembodiment of the invention. During processing of device, the substratehas been removed, for example, by an etching step. A topside or abackside of device 116 may be mounted on, or bonded to, a carrier (notshown, See FIG. 24) which provides support and rigidity for the device.In this illustrative embodiment, the entire backside of a transitionlayer 15 b having a constant composition (e.g., an intermediate layer ofa gallium nitride alloy, aluminum nitride, or an aluminum nitride alloy)is exposed. A compositionally-graded transition layer 15 a is formed onconstant composition transition layer 15 b. It should also be understoodthat, in some embodiments, constant composition transition layer 15 b isabsent (or otherwise positioned) and compositionally-graded transitionlayer 15 a is exposed. In some cases, a passivating layer may be formedon transition layer 15 b; or, transition layer 15 b may be mounted onthe surface of a packaging material. The illustrative embodiment may beparticular useful in order to maximize light extraction from the device.Device 116 also has two topside contacts 114 a, 114 b and no backsidecontacts. The absence of backside contacts also enhances light emission.It should be understood that light emitting device 116 may have anysuitable layer arrangement including the layer arrangements (or aportion thereof) of the LED embodiments described herein.

FIG. 16 illustrates a light emitting device 118 according to anotherembodiment of the invention that includes reflector region 120 locatedbelow the active region 97. Reflector region 120 reflects a substantialportion of the light (indicated by arrows) emitted from the activeregion in the direction of the topside of the device. Therefore, thisstructure enhances light emission out of the topside of the device. Itshould be understood that light emitting device 116 may have anysuitable layer arrangement including the layer arrangements (or aportion thereof) of the LED embodiments described herein.

FIG. 17 illustrates a light emitting device 122 according to anotherembodiment of the invention that includes reflector region 120 locatedabove the active region 97. Reflector region 120 reflects a substantialportion of the light (indicated by arrows) emitted from the lightemitting region in the direction of the backside of the device.Therefore, this structure enhances light emission out of the backside ofthe device. It should be understood that light emitting device 122 mayhave any suitable layer arrangement including the layer arrangements (ora portion thereof) of the LED embodiments described herein.

FIG. 19 illustrates a light emitting device 130 according to anotherembodiment of the invention that includes a first reflector region 120 aformed within via 24. Device 130 has two topside contacts 114 a, 114 b.Reflector region 120 a may be, for example, a reflective metal layer. Itshould be understood that reflector region 120 a is not an electricalcontact even when it comprises a conductive metal because it is notdesigned to be contacted by a power source. In the illustrativeembodiment, device 130 may include a second reflector region 120 bformed over the via which may be a Distributed Bragg Reflector (DBR)that includes a number of semiconductor or dielectric layers. Device 130includes two reflector regions to increase the ability of the device toreflect generated light in the desired direction. It should beunderstood, however, that other devices may include only one reflectorregion which may be formed within the via or may be formed over the via.It should be understood that light emitting device 130 may have anysuitable layer arrangement including the layer arrangements (or aportion thereof) of the LED embodiments described herein.

FIG. 20 illustrates a light emitting device 136 that has been flippedduring use so that backside 22 faces upward and topside 18 facesdownward. Topside contact 114 b also functions as a reflector regionthat can upwardly reflect light generated in region 97. The device alsoincludes a second reflector region 120 b which may be a DistributedBragg Reflector (DBR) that includes a number of semiconductor ordielectric layers. Device 136 includes two reflector regions to increasethe ability of the device to reflect generated light in the desireddirection. It should be understood, however, that other devices mayinclude only one reflector region which may be an electrical contact(e.g., topside contact 114 b) or a layer(s) within the structure of thedevice. It should be understood that light emitting device 136 may haveany suitable layer arrangement including the layer arrangements (or aportion thereof) of the LED embodiments described herein.

FIG. 21 illustrates an LED 132 designed to emit ultra-violet light, forexample, having a wavelength between about 200 nm and about 410 nm. LED132 includes gallium nitride material device region 14 formed ontransition layer 15. Transition layer 15 may be compositionally-gradedand is formed on silicon substrate 12. In the illustrative embodiment,the following layers comprise gallium nitride material device region 14in succession: a silicon-doped Al_(x)Ga_((1-x))N layer 134 (e.g.,containing 0-100% Al), a silicon-doped Al_(x)Ga_((1-x))N layer 136(e.g., containing 20-80% by weight Al), an active region 138, amagnesium-doped Al_(x)Ga_((1-x))N layer 140 (e.g., containing 20-80% byweight Al), and a magnesium-doped Al_(x)Ga_((1-x))N layer 141 (e.g.,containing 0-80% by weight Al). Active region 138 may be a single ormultiple quantum well (e.g., Al_(x)Ga_((1-x))N/GaN,Al_(x)Ga_((1-x))N/Al_(y)Ga_((1-y))N,Al_(x)Ga_((1-x))N/Al_(y)In_((1-y))N, orAl_(x)In_(y)Ga_((1-x-y))N/Al_(a)In_(b)Ga_((1-a-b))N). In some cases,layers 134, 136, 140, 141 may be superlattices and may includedelta-doped regions to enhance conductivity. Topside contact 16 isformed of a metal on a p-type region and backside contact 20 is formedof a metal on an n-type region. It should be understood that LEDs havinga variety of different structures may also be provided according to theinvention including other types of LEDs that emit UV light and LEDs thatemit visible light.

FIGS. 23A-23K show a series of plane-view cross-sections of the activeregions 97 of a series of opto-electronic devices according toadditional embodiments of the present invention. A plane-viewcross-section is the cross-section of the active region taken in theplane of the active region (See FIG. 24). Though FIGS. 23A-23K are takenwith respect to the active region 97 shown in FIG. 24, it should beunderstood that active regions having the illustrated plane-viewcross-sections also may be formed in any other suitable device structureincluding the other device structures described herein.

As seen in the figures, the devices of the invention may include activeregions having a variety of plane-view cross-sections that may bedesigned for specific applications. In some cases, the plane-viewcross-sections are rectangular or square (FIGS. 23A and 23B).Advantageously, certain embodiments of the invention, also enablesformation of non-rectangular plane-view cross-sections includingcircular (FIG. 23C), star-shaped (FIG. 23D), hexagon (FIG. 23E),pentagon (FIG. 23F), octagon (FIG. 23G), triangular (FIG. 23H),trapezoid (FIG. 23I), diamond (FIG. 23J) and H-shaped (FIG. 23K),amongst others.

Active regions having non-rectangular plane-view cross-sections mayimprove light extraction over conventional square or rectangularcross-sections by reducing internal reflective losses. Advantageously,the shape of the cross-sections may be tailored for the specific deviceto optimize light extraction efficiency. In some embodiments, it may bepreferred to enhance light extraction for the active region to have anon-rectangular, non-circular plane view cross-section. A variety ofother active region cross-sections may also be utilized in accordancewith the present invention.

Active regions having non-rectangular plane-view cross-sections may beformed using an etching process. In some cases, the etching process usedto form the active regions may be the same etching process used toseparate individual devices processed on the same wafer from oneanother, as described above. This etching process may be used to formthe active region and separate devices, for example, when the substrateis silicon because silicon may be readily etched, in contrast to othertypes of substrates (e.g., sapphire and silicon carbide) which typicallyrequire the use of a dicing operation to separate devices. In cases whenthe etching process used to form the active region is the same as theetching process used to separate individual devices processed on thesame wafer, the active region may have the same plane-view cross-sectionas other non-active regions on the device (including other layers andthe substrate), as well as the overall die shape. It should beunderstood that though the same etching process is used to form theactive region and to separate individual devices processed on the samewafer, different etching chemistries may be used at various stagesduring this process, for example, to etch through different layers.

It should be understood that active regions having non-rectangularplane-view cross-sections may be formed in an etching process that doesnot separate individual devices processed on the same wafer from oneanother. In these cases, the individual devices may be separated usingconventional dicing steps, for example, to form devices having arectangular die shape. In these cases, the active region may have anon-rectangular plane-view cross-section, while non-active regions mayhave a different plane-view cross-section (including a rectangularplane-view cross-section).

FIG. 25 shows a light emitting device 160 according to anotherembodiment of the present invention. During processing of device 160,the substrate has been removed, for example, by an etching step. In thisillustrative embodiment, device 160 includes a topside contact 16 and abackside contact 20. Topside contact 16 also functions as a reflectorregion. Backside contact 20 is formed on a transition layer 15 b havinga constant composition. A compositionally-graded transition layer 15 ais formed on constant composition transition layer 15 b. Transitionlayers 15 a, 15 b are sufficiently conductive to enable conductionbetween topside contact 16 and backside contact 20. In some cases,transition layers 15 a, 15 b may be doped to achieve sufficientconductivity. It should also be understood that, in some embodiments,other transition layer arrangements are possible including thosedescribed above. In the illustrative embodiment, a topside of the deviceis mounted to a carrier 162. Carrier 162, for example, may be a wafer(e.g., silicon or GaAs). Carrier 162 provides support and rigidity forthe device. It should be understood that in other embodiments carrier162 may be mounted on a bottom side of the device. In other cases, acontact may be formed on the carrier.

It should be understood that light emitting device 160 may have anysuitable layer arrangement including the layer arrangements (or aportion thereof) of the LED embodiments described herein.

Those skilled in the art would readily appreciate that all parameterslisted herein are meant to be exemplary and that the actual parameterswould depend upon the specific application for which the semiconductormaterials and methods of the invention are used. It is, therefore, to beunderstood that the foregoing embodiments are presented by way ofexample only and that, within the scope of the appended claims andequivalents thereto the invention may be practiced otherwise than asspecifically described.

1. A semiconductor device comprising: a substrate; and a gallium nitridematerial region formed over the substrate, wherein the semiconductordevice has at least one via extending from a first side of thesemiconductor device, wherein the via is free of an electrical contactformed therein.